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Name - Ashish Panchal (22ENG7ECE0001)

Branch - Electronics & Communication Engineering

Faculty - Faculty of Engineering & Technology

Date of Registration - 2nd December 2022

Supervisor - Dr. Nidhi Tiwari, Associate Professor.

Date of Ph.D. Viva - 17th April 2026 (Friday) at 10.00 AM.

Title - Design and Performance Analysis of SRAM memory Cell for Low Power Application


[1]. Ashish Panchal, Nidhi Tiwari, and Vaibhav Neema, “Read/write Improved Low Leakage 10TP SRAM Cell for Battery Operated Biomedical Applications,” 10th International Conference on Microelectronics Circuits and Systems, on Micro2023.

[2]. Ashish Panchal, Sneha Nagar, Nidhi Tiwari, and Vaibhav Neema, “2.67aJ/bit Write Energy Efficient GCC10T SRAM Cell for IoT applications,” 11th International Conference on Microelectronics Circuits, and Systems, on Micro2025. 
 
International Journals

[3]. A. Panchal, p. Sharma, N. Tiwari, A. Gupta, Tiwari N. Neema, R. Sindal, “Improved reliability single loop single feed 7T SRAM cell for biomedical applications,” Memories-Materials, Devices, Circuits and Systems. 2023 vol.4, 100057. Scopus, Cite Score 4.4. https://doi.org/10.1016/j.memori.2023.100057.

[4]. A. Panchal, N. Tiwari, V. Neema, “Comparative study of decoupled read buffer SRAM memory cell for improve read noise margin,” Materials Today: Proceedings (2023). Scopus, Cite Score 3.8. https://doi.org/10.1016/j.matpr.2023.03.494

[5]. A. Panchal, N. Tiwari, V. Neema, “Half selection resilient energy efficient HSR11T SRAM cell at subthreshold region with 0.09 fJ/bit hold energy,” Engineering Research Express. 2025, vol. 7(3), 035348. SCI, IF 1.5.
10.1088/2631-8695/adf8bb