workshop on Synopsys under the C2S (Chips to Startup) Project
The Research & Development Cell, SAGE University Indore, is pleased to announce a hands-on workshop on Synopsys under the C2S (Chips to Startup) Project. This workshop aims to provide participants with practical exposure to industry-standard Electronic Design Automation (EDA) tools and FPGA-based design methodologies that are widely used in semiconductor, VLSI, and embedded system industries.
Participants will gain insights into tool installation, design workflows, and experimental implementation using Cadence platforms. The session will be conducted by experienced resource persons from Shri Vaishnav Vidyapeeth Vishwavidyalaya, offering valuable guidance on semiconductor design practices and emerging opportunities in the chip design ecosystem.
Resource Persons
Dr. Preet jain Sir, Professor, Shri Vaishnav Vidyapeeth Vishwavidyalaya indore,
Workshop Details
Date: 04 July 2026
Time: 11:00 AM – 3:30 PM
Venue: A Block, G23
Certificates will be provide to the all registered participants
Key Takeaways
Installation and configuration of Synopsys tool
Understanding VLSI and semiconductor design workflows
Hands-on Synopsys experiments
Exposure to industry-relevant EDA tools and methodologies
Learning opportunities under the C2S Project......
